Fast cycle RAM and data readout method therefor

ABSTRACT

A row access command and column access command are supplied as one packet to an FCRAM in two successive clock cycles in order to shorten random access time and random cycle time. At this time, definition of the read/write operation is made by use of a first command and a decode address of a memory cell array is fetched in response to the first command. When the decode address of the memory cell array is fetched in response to the first command, command control pins of the conventional SDR/DDR-SDRAM are used as address pins.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based upon and claims the benefit of priorityfrom the prior Japanese Patent Application No. 11-373531, filed Dec. 28,1999, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] This invention relates to a semiconductor memory device and adata readout method therefor and more particularly to a fast cyclesynchronous DRAM (SDR-FCRAM) having a function of rapidlyreading/writing random data from or into a memory cell array insynchronism with a clock signal and a data readout method for a doubledata rate synchronous DRAM (DDR-FCRAM) for realizing the data transferrate twice that of the above DRAM.

[0003] In order to enhance the data access speed of a DRAM to that of anSDRAM and attain a large data band width (the number of data bytes foreach unit time) by use of a high clock frequency (cycle time tCK), asynchronous DRAM (SDRAM) is invented and is already put into practicefrom the 4-Mbit or 16-Mbit DRAM generation.

[0004] Recently, in order to further enhance the operation speed of theSDRAM, a double data rate SDRAM which is operated at the data transferrate twice that of the conventional SDRAM by operating the same insynchronism with both of the rise edge and fall edge of a clock signalis proposed and actively commercialized.

[0005] In order to enhance the data transfer rate, the data bandwidth isactively increased, but it is difficult to enhance the speed of randomaccess to cell data in a memory core, that is, the sped of data accessto a row address which has been changed to indicate a different row.This is because the cycle time (random cycle time=tRC) of the memorycore cannot be greatly reduced since a certain period of time (which isreferred to as core latency) is required for the destructive readout andamplifying operation inherent to the DRAM and the precharge operationprior to the next access to the memory core.

[0006] In order to solve the above problem, a so-called fast cycle RAM(FCRAM) in which access to the memory core and the precharge operationthereof are pipelined to reduce the random cycle time to half of that ofthe conventional DRAM or less is proposed and will be started to becommercialized mainly in the network field in which random data of arouter or LAN switch using SRAMs in the prior art is transferred at highspeed.

[0007] The basic system of the data readout operation of the FCRAM isdescribed in International Application (International Publication NumberWO98/56004 (Fujioka et al.)) based on Jpn. Pat. Appln. Nos. H09-145406,H09-215047 and H09-332739 used as the basic application, for example.

[0008] This invention is to improve the data readout operation of theFCRAM defined in the above International Application and relates to theimprovement of a method for supplying a row access instruction andcolumn access instruction.

[0009] First, the basic system and the operation of data readout in theFCRAM disclosed in the above International Application are brieflyexplained with reference to FIGS. 1 to 5. FIGS. 1 to 3 correspond toFIGS. 4 to 6 in International Publication No. WO98/56004.

[0010]FIG. 1 is a principle diagram for reducing or shortening therandom cycle time tRC in the FCRAM and shows a row-series pipelineoperation. FIG. 2 is a detail timing chart of an internal operation forrealizing the pipeline operation. FIG. 3 is a timing chart forillustrating the operation for enhancing the row access speed by theself-precharge operation. FIG. 4 shows an example of a command inputmethod at the readout time defined in the FCRAM. FIG. 5 is a commandstatus diagram in the data readout system described in the aboveInternational Application.

[0011] In FIGS. 2 and 3, WL indicates the potential of a word line, BL,{overscore (BL)} indicate the potentials of paired bit lines, SAEindicates an enable signal of a bit line sense amplifier, CSL indicatesa signal (which is the potential of the column selection line) selectedaccording to a column address, for transferring data on the bit linepair BL, {overscore (BL)} amplified by the bit line sense amplifier to aperipheral data bus, EQL is a precharge/equalizing signal for the pairedbit lines, ACT indicates a row access command and RD is a column accesscommand.

[0012] In FIG. 4, BA0 to BA3 indicate a bank address, A0 to A10 indicatean address, UA indicates an upper address, LA0 to LA9 indicate a loweraddress, and LA1, LA0 among the lower address LA0 to LA9 indicate aburst address.

[0013] In FIG. 5, DESL indicates a deselect operation, POWER DOWNindicates a power down operation, MODE REGISTER indicates a moderegister, WRITE indicates a write operation, IDLE indicates a 50% adderlatched, READ indicates a read operation, AUTO-REFRESH indicates anauto-refresh operation, SELF-REFRESH indicates a self-refresh operation,PDEN indicates a power down command, PDEX indicates a power down releasecommand, MRS indicates a mode register set command, ACT indicates a rowaccess command (first command), RD indicates a read column accesscommand (second command), REF indicates a auto refresh command, WRindicates a write access command, SELF indicates a self-refresh commandand SELFX indicates a self-refresh release command.

[0014] In order to enhance the speed of random data readout from amemory cell array, it is considered that the following three stages arepipelined as shown in FIG. 1:

[0015] (1) command decoding operation and peripheral circuit operation;

[0016] (2) sense amplification operation; and

[0017] (3) data output operation.

[0018] In this case, in the DRAM, the longest time is required for thestage (2), that is, for “word line selection cycle”+“sense amplifierdriving cycle”+“reset cycle (sense amplification cycle)” as shown in thetiming chart of FIG. 2. In order to reduce the time to minimum, insteadof decoding the row address, subjecting data read out from the memorycell MC connected to the selected word line WL to the differentialamplification by the bit line sense amplifier S/A, terminating therestore operation, and then successively opening the column selectiongates in response to a plurality of column addresses by use of thecolumn selection lines CSL to make burst access as in the conventionalSDRAM, it is necessary to read out data of a necessary burst length tothe bit line sense amplifier S/A so as to instantly terminate the senseamplifying operation (stage (2)) by simultaneously opening a pluralityof column selection gates larger in number than the SDRAMs after therestore operation is terminated and then effect the reset (precharge)cycle in the shortest time while the data outputting operation (stage(3)) is being effected.

[0019] In order to realize the above operation, the operation based onthe timing chart shown in FIG. 3 is required. The feature of theoperation shown in FIG. 3 is that a row access command ATC and columnaccess command RD (in this case, it indicates “read”) are supplied tothe FCRAM as one packet. The commands are supplied in response tosuccessive clock input pulses so that the command interval will becomeminimum and the command cycle time can be reduced. By fetching the rowaccess command ACT and column access command RD in synchronism with thetwo successive clocks, it becomes possible to fetch a column address CAiwhich is fetched at the same time as the column access command RD atearlier timing, thereby making it possible to select a column selectionline CSL at earlier timing. Further, as a secondary effect, part of thecolumn address CAi can be used as an address for dividing the senseamplifiers, and therefore, the number of sense amplifiers to be operatedis limited in comparison with the conventional DRAM and the operationspeed of the stage (2) can be enhanced.

[0020] As shown in FIG. 5, in the above readout method, a row address islatched in response to input of a first command ACT in the deselectstate (standby state) to start the operation of the row-seriesperipheral circuit. Next, part of the column address CAi is used as arow address for decoding the sense amplifier by use of the secondcommand RD (column access command for “read”) or {overscore (WR)}(column access command for “write”) and access to the thus limitedmemory core is started. Then, after termination of the access, thedeselect state is automatically restored.

[0021] However, the above command system has the following problem. Thatis, since the row access command is supplied only for decoding thecommand and starting the operation of the peripheral circuit, theoperations of the stages (2) and (3) cannot be started until a columnaccess command RD (“read” in this case) is input one cycle after thepresent cycle. Therefore, the random cycle time tRC is defined by aninterval between the row access commands ACT and ACT or between thecolumn access commands RD and RD and can be reduced without causing anyproblem, but data access from the row access command ACT, that is,random access time tRAC will contain an extra one clock cycle.

[0022] In order to cope with this, in the above InternationalApplication, a system for simultaneously inputting the row accesscommand ACT and column access command RD is proposed. However, in thissystem, since the command decoding operation is extremely complicatedand the logic construction of the internal circuit becomes larger, thereoccurs a possibility that extra delay time occurs in the front half partof the random access time tRAC. Further, since the command decodingoperation becomes complicated, the number of input pins of the devicemay be increased in many cases and there occurs a possibility that thepackage size will be increased and the cost will rise.

[0023] As described above, in the conventional semiconductor memorydevice, if the row access command and column access command are given asone packet in order to enhance the speed of random data readout from thememory cell array, data access from the row access command, that is, therandom access time will contain an extra one clock cycle without fail.

[0024] In order to solve this problem, a system for simultaneouslyinputting the row access command and column access command is proposed,but in this case, since the command decoding operation is extremelycomplicated and the logic construction of the internal circuit becomeslarger, there occurs a possibility that extra delay time occurs in thefront half part of the random access time. Further, there occurs apossibility that the package size will be increased and the cost willrise due to an increase in the number of input pins of the device.

BRIEF SUMMARY OF THE INVENTION

[0025] Accordingly, an object of this invention is to provide asemiconductor memory device and a data readout method therefor capableof enhancing the readout speed of random data from a memory cell arraywithout degrading the random access time.

[0026] Further, another object of this invention is to provide asemiconductor memory device and a data readout method therefor capableenhancing the readout speed of random data from a memory cell arraywhile the command decoding operation is suppressed from beingcomplicated and the logic construction of the internal circuit issuppressed from becoming larger.

[0027] In addition, still another object of this invention is to providea semiconductor memory device and a data readout method therefor capableenhancing the readout speed of random data from a memory cell arraywhile an increase in the cost due to an increase in the number of pinsand an increase in the package size is suppressed.

[0028] The above object of this invention can be attained by asemiconductor memory device in which first and second commands are inputto effect a read/write operation of random data with respect to a memorycell array in synchronism with a clock signal and a row access commandand a column access command for data readout are supplied as one packetin two successive clock cycles, comprising a first pin supplied with asignal for distinguishing a read command and a write command; secondpins supplied with upper-side and lower-side decode addresses; acontroller to which a signal indicating that the read command is inputand a signal indicating that the write command is input based on thesignal input to the first pin are supplied; a first command decodercontrolled by an output signal of the controller, for defining one ofthe readout and write operations by use of the first command, fetchingan upper-side decode address of a memory cell array via the second pinand decoding the first command; and a lower-side command decodercontrolled by an output signal of the controller, for fetching alower-side decode address of the memory cell array via the control pinsin response to the second command and decoding the lower-side decodeaddress.

[0029] A data readout method for a semiconductor memory device in whicha row access command and a column access command for data readout aresupplied as one packet in two successive clock cycles, comprising afirst step of inputting first command in response to a change of a clocksignal to determine one of readout and write operations and fetching anupper-side decode address of a memory cell array to operate a row-seriesperipheral circuit, select a word line and drive a sense amplifier; anda second step of inputting a second command in response to a change ofthe clock signal one cycle after the present cycle to fetch a lower-sidedecode address of the memory cell array, release selection of the wordline and transfer data.

[0030] A data readout method for a semiconductor memory device in whichfirst and second commands are input to effect a read/write operation ofrandom data with respect to a memory cell array in synchronism with aclock signal and a row access command and a column access command fordata readout are supplied as one packet in two successive clock cycles,comprising the steps of defining one of readout and write operations andfetching an upper-side decode address of the memory cell array inresponse to the first command; and fetching a lower-side decode addressof the memory cell array in response to the second command.

[0031] A data readout method for a semiconductor memory device in whichfirst and second commands are input to effect a read/write operation ofrandom data with respect to a memory cell array in synchronism with aclock signal, comprising the steps of fetching a row address in responseto input of the first command next to the standby state; and directlysupplying a read command (Read with Auto-close) instead of a row accesscommand for starting the operation of a peripheral row-series circuit.

[0032] A data readout method for a semiconductor memory device in whichfirst and second commands are input to effect a read/write operation ofrandom data with respect to a memory cell array in synchronism with aclock signal, comprising the steps of fetching a row address in responseto input of the first command next to the standby state; and directlysupplying a write command (Write with Auto-close) instead of a rowaccess command for starting the operation of a peripheral row-seriescircuit.

[0033] With the above construction and method, since the readoutoperation or write operation can be determined by the first command, notonly the operation of the peripheral circuit but also the operation ofthe memory core can be started at the same time as the operation forfetching the row address and the start timing of the random accessbecomes earlier in comparison with a case wherein the start timing ofthe operation of the memory core is determined according to the secondcommand as in the conventional case, and as a result, the random accesstime is automatically made shorter by one clock cycle.

[0034] Further, since the readout operation or write operation can bedetermined by the first command, it is only required to fetch thelower-side decode address of the memory cell array in response to thesecond command. Therefore, the process for selecting the columnselection line and outputting data becomes earlier than in theconventional case, high-speed random access time can be realized, and asa result, time from releasing of selection of the word line toprecharging of the bit line pair can be shortened, that is, high-speedrandom cycle time can be realized by terminating transfer of data to theperipheral portion at earlier timing.

[0035] In addition, if low-side and upper-side decode addresses of thememory cell array are input to existing control pins used as addresspins, the speed of random data readout from the memory cell array can beenhanced while an increase in the cost due to an increase in the numberof pins and an increase in the package size is suppressed. As thecontrol pins, in the case of the SDR-DDRAM or DDR-SDRAM, it is suitableto use a write enable pin and column address strobe pin.

[0036] Further, if activation of the column selection line is controlledby use of a gating signal, it is possible to read out cell data to anoutput pin after the sense operation is stabilized in a case wherein thecycle time is short.

[0037] Additional objects and advantages of the invention will be setforth in the description which follows, and in part will be obvious fromthe description, or may be learned by practice of the invention. Theobjects and advantages of the invention may be realized and obtained bymeans of the instrumentalities and combinations particularly pointed outhereinafter.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

[0038] The accompanying drawings, which are incorporated in andconstitute a part of the specification, illustrate presently preferredembodiments of the invention, and together with the general descriptiongiven above and the detailed description of the preferred embodimentsgiven below, serve to explain the principles of the invention.

[0039]FIG. 1 is a schematic diagram showing the pipeline operation of arow series, for illustrating the principle of the operation for reducingthe random cycle time in a conventional semiconductor memory device(FCRAM);

[0040]FIG. 2 is a detail timing chart of an internal operation, forrealizing the pipeline operation shown in FIG. 1;

[0041]FIG. 3 is a detail timing chart of an internal operation, forrealizing the improved pipeline operation of a conventional FCRAM;

[0042]FIG. 4 is a diagram showing an example of a command input methodat the readout time which is defined in the conventional FCRAM;

[0043]FIG. 5 is a command status diagram of the conventional FCRAM;

[0044]FIG. 6 is a command status diagram of an FCRAM, for illustrating asemiconductor memory device according to an embodiment of thisinvention;

[0045]FIGS. 7A and 7B are diagrams for illustrating the functions ofcommands shown in FIG. 6;

[0046]FIG. 8 is a top plan view showing the assignment of pins of apackage of the FCRAM;

[0047]FIG. 9 is a circuit diagram showing an example of the concreteconstruction of a controller for controlling the operation of a commanddecoder;

[0048]FIG. 10 is a circuit diagram showing an example of the concreteconstruction of an upper-side command decoder;

[0049]FIG. 11 is a circuit diagram showing an example of the concreteconstruction of a lower-side command decoder;

[0050]FIG. 12 is a timing chart for illustrating the operations of thecontroller and command decoder shown in FIGS. 9 to 11;

[0051]FIGS. 13A and 13B are timing charts for illustrating the operationfor reading out data in a random fashion from a memory cell array in thesemiconductor memory device according to the embodiment of thisinvention;

[0052]FIG. 14 is a timing chart for illustrating an example of thedefinition of the random access time in a first command (read) accordingto cycle time;

[0053]FIG. 15A is a circuit diagram showing an example of the concreteconstruction of a gating signal generating circuit;

[0054]FIG. 15B is a circuit diagram showing another example of theconcrete construction of a gating signal generating circuit;

[0055]FIG. 15C is a circuit diagram showing an example of the concreteconstruction of a column decoder;

[0056]FIGS. 16A and 16B are timing charts showing the random datareadout operation of the conventional semiconductor memory device, forillustrating the general operations of the conventional semiconductormemory device and the semiconductor memory device according to thisinvention in comparison with each other; and

[0057]FIG. 17 is a timing chart showing the random data readoutoperation of the semiconductor memory device according to thisinvention, for illustrating the general operations of the conventionalsemiconductor memory device and the semiconductor memory deviceaccording to this invention in comparison with each other.

DETAILED DESCRIPTION OF THE INVENTION

[0058]FIGS. 6, 7A and 7B diagrams for illustrating a semiconductormemory device according to an embodiment of this invention. FIG. 6 is acommand status diagram of an FCRAM (SDR/DDR-SDRAM) and FIGS. 7A and 7Bare function tables thereof. That is, as shown in FIG. 6, a row addressis fetched in response to input of a first command next to the standbystate (STANDBY) and a read command (Read with Auto-close) RDA or writecommand (Write with Auto-close) WRA is directly supplied instead of theconventional row access command ACT for starting the operation of theperipheral row-series circuit. As is clearly understood from thefunction tables shown in FIGS. 7A and 7B, command input is accepted whenthe potential of a chip select pin CS provided on the SDR/DDR-SDRAM isset to the “L” level and distinction between the read and write commandsis made by additionally providing an FN pin for defining the type of acommand and using the level of a signal supplied to the pin. In thisexample, if a read command is supplied, the potential of the FN pin isset to the “H” level and if a write command is supplied, it is set tothe “L” level.

[0059] In the conventional SDR/DDR-SDRAM, a divisional decoding rowaddress for sense amplifiers which is supplied in a second command canbe supplied in a first command in this invention. However, since thenumber of pins of a standard package is limited, existing control pinsare used as address pins to suppress an increase in the number of pins.In this example, a {overscore (WE)} (write enable) pin and {overscore(CAS)} (column address strobe) pin in the SDR/DDR-SDRAM are used asaddress pins A13, A14. Thus, the advantage that the number of divisionsof the sense amplifiers to be decoded is increased and the number ofsense amplifiers to be activated is limited can be maintained.

[0060] The assignment of pins on the package of the FCRAM, based on theabove system is shown in FIG. 8. This example is a 66-pin TSOP (ThinSmall Outline Package) package which is standardized by JEDEC (jointElectron Device Engineering Council), and a row address RA0-i (sincedistinction of row/column is not necessary any more, an address fetchedby use of the first command is referred to as an upper address UA and anaddress fetched by use of the second command is referred to as a loweraddress LA in FIG. 8) simultaneously supplied form the original{overscore (WE)}, {overscore (CAS)} pins in response to the rise edge ofa clock of the first command is fetched, and if the first command is aread command, a word line WL is selected according to the row address toread out data from the memory cell MC to a bit line pair BL, {overscore(BL)} and the data is amplified by the bit line sense amplifier S/A. Theoperation described above is completed by input of the first command. InFIG. 8, {overscore (WE)} and {overscore (CAS)} are changed according toinput of an address. Further, UDM and LDM are changed according to NCand {overscore (RAS)} is changed according to FN.

[0061] Next, a lower address latch command LAL, mode register setcommand MRS and auto-refresh command REF are supplied as the secondcommand one clock cycle after inputting of the read command RDA or writecommand WRA. At this time, since the read mode is determined by thefirst command and it is only necessary to supply a column address andoutput data, no complicated command set is required.

[0062] In FIG. 6, a case wherein the potential of the chip selection pin{overscore (CS)} is set at the “H” level and a column address CA0-j(lower address LA) is fetched from the address pins is explained. As aresult, at the time of input of the second command, a column address issimply fetched, a corresponding column selection line CSL is selectedand data amplified by the bit line sense amplifier S/A is transferred toan MDQ line pair according to the first command, then amplified by a DQread buffer DQRB again and finally output from an output pin DQ.

[0063] As shown in FIGS. 9 to 11, for example, the command decoder forrealizing the above operation includes a controller, a decoder for thefirst command and a decoder for the second command. FIG. 9 is a circuitdiagram showing an example of the concrete construction of thecontroller for controlling the operation of the command decoders. FIG.10 is a circuit diagram showing an example of the concrete constructionof an upper-side command decoder and FIG. 11 is a circuit diagramshowing an example of the concrete construction of a lower-side commanddecoder.

[0064] As shown in FIG. 9, the controller includes clocked inverters 11to 16, inverters 17 to 27, NOR gate 28 and NAND gates 29 to 32. A signalbCSIN obtained by buffering an external input {overscore (CS)} in theinternal portion is supplied to an input terminal of the clockedinverter 11 controlled by a signal CLKIN obtained by buffering anexternal input clock in the internal portion. The output terminal of theclocked inverter 11 is connected to the input terminal of the inverter17 whose output terminal is connected to one-side input terminals of theNOR gate 28 and NAND gate 29. The output terminal of the NOR gate 28 isconnected to the input terminal of the inverter 18. The output terminalof the clocked inverter 12 controlled by the signal CLKIN is connectedto the input terminal of the inverter 17 and the input terminal thereofis connected to the output terminal of the inverter 17.

[0065] Further, the signal CLKIN is supplied to the input terminal ofthe inverter 19 and the output terminal of the inverter 19 is connectedto the other input terminal of the NOR gate 28 and the input terminal ofthe inverter 20. The output terminal of the inverter 20 is connected tothe other input terminal of the NAND gate 29. The output terminal of theNAND gate 29 is connected to the input terminal of the inverter 21.Then, a signal bCSLTC is output from the output terminal of the inverter18 and a signal NOPLTC is output from the output terminal of theinverter 21.

[0066] A signal bCOLACTRU indicating that an RDA command is input and asignal bCOLACTWU indicating that an WRA command is input are supplied tothe respective input terminals of the NAND gate 30. The output terminalof the NAND gate 30 is connected to the input terminal of the inverter13 controlled by a signal bCK (equivalent to an inverted signal of thesignal CLKIN obtained by buffering an external input clock in theinternal portion). The output terminal of the clocked inverter 13 isconnected to the input terminal of the inverter 22 and the outputterminal of the inverter 14 controlled by a signal CK (equivalent to thesignal CLKIN obtained by buffering an external input clock in theinternal portion). The output terminal of the inverter 22 is connectedto the input terminals of the clocked inverters 14, 15 controlled by thesignal CK. The output terminal of the clocked inverter 15 is connectedto the input terminal of the inverter 23 and the output terminal of theclocked inverter 16 controlled by the signal bCK. The output terminal ofthe inverter 23 is connected to the input terminal of the inverter 23and the input terminal of the clocked inverter 16. The output terminalof the inverter 24 is connected to the input terminal of the inverter 25whose output terminal is connected to the input terminal of the inverter26. A signal bACTUDSB is output from the output terminal of the inverter26.

[0067] One input terminal of the NAND gate 31 is supplied with a signalbCOLACTRU and the other input terminal thereof is connected to theoutput terminal of the NAND gate 32. One input terminal of the NAND gate32 is supplied with a signal bCOLACTWU and the other input terminalthereof is connected to the output terminal of the NAND gate 31. Asignal FCREAD is output from the output terminal of the NAND gate 31 anda signal PCWRITE is output from the output terminal of the inverter 27whose input terminal is connected to the output terminal of the NANDgate 31.

[0068] As shown in FIG. 10, an upper-side command decoder includesinverters 41 to 45, NAND gate 46 and NOR gate 47. The input terminals ofthe inverters 41, 42 are respectively supplied with a signal bCSLTCobtained by buffering an external input {overscore (CAS)} (FN) in theinternal portion and latching the same by a half clock and a signalbRASLTC obtained by buffering an external input {overscore (RAS)} (FN)in the internal portion and latching the same by a half clock. The firstinput terminal of the NAND gate 46 is connected to the output terminalof the inverter 41, the second input terminal thereof is connected tothe output terminal of the inverter 42 and the third input terminalthereof is supplied with a signal bACTUDSB from the above controller.The output terminal of the NANP gate 46 is connected to the inputterminal of the inverter 43 whose output terminal is connected to theinput terminal of the inverter 44. The first input terminal of the NORgate 47 is supplied with the signal bACTUDSB from the above controller,the second input terminal thereof is connected to the output terminal ofthe inverter 42 and the third input terminal thereof is supplied withthe signal bCSLTC. The output terminal of the NOR gate 47 is connectedto the input terminal of the inverter 45. A signal bCOLACTWU output fromthe output terminal of the inverter 44 is supplied to the controller anda signal bCOLACTRU output from the output terminal of the inverter 45 issupplied to the controller. In the circuit shown in FIG. 10, the numberof stages is reduced by supplying the various signals to the NOR gate 47so as to shorten the random access time tRAC.

[0069] As shown in FIG. 11, the lower-side command decoder includes NORgates 51, 52, inverters 53 to 61 and NAND gates 62 to 65. The inputterminals of the NOR gate 51 are supplied with the respective signalsbACTUDSB and PCWRITE output from the controller. The input terminals ofthe NOR gate 52 are supplied with the respective signals bACTUDSB andPCREAD output from the controller. One input terminal of the NAND gate62 is supplied with a signal NOPLTC output from the controller and theother input terminal thereof is connected to the output terminal of theNOR gate 51. One input terminal of the NAND gate 63 is supplied with asignal NOPLTC output from the controller and the other input terminalthereof is connected to the output terminal of the NOR gate 52. Oneinput terminal of the NAND gate 64 is connected to the output terminalof the inverter 53 and the other input terminal thereof is connected tothe output terminal of the NOR gate 51. One input terminal of the NANDgate 65 is connected to the output terminal of the inverter 53 and theother input terminal thereof is connected to the output terminal of theNOR gate 52. The output terminals of the NAND gates 62 to 65 arerespectively connected to the input terminals of the inverters 54 to 57whose output terminals are respectively connected to the input terminalsof the inverters 58 to 61. A signal bCOLACTR indicating that a loweraddress latch command LAL is input in a clock cycle next to the readcommand RDA is output from the output terminal of the inverter 58, asignal bCOLACTW indicating that the command LAL is input in a clockcycle next to the write command WRA is output from the output terminalof the inverter 59, a signal bMSET indicating that a command MRS isinput in a clock cycle next to the command RDA is output from the outputterminal of the inverter 60, and a signal bREFR indicating that acommand REF is input in a clock cycle next to the command WRA is outputfrom the output terminal of the inverter 61.

[0070] The operation with the above construction is explained withreference to the timing chart shown in FIG. 12. First, the signalsbCSLTC and bRASLTC are changed according to the states of the respectivepotentials VBCS and VBRAS of the {overscore (CS)} pin and {overscore(RAS)} pin when the first command is input and the signal bCOLACTWU orbCOLACTRU is set to the “L” level (the former one in the case of FIG.12). At this time, a corresponding one of the signals FCWRITE and FCREADin the controller is set to the “H” level. The signal bACTUDSB is set toand maintained at the “L” level for one clock cycle from the fall of theclock signal after the first command is input so that the second commandcan be accepted. Further, the signal NOPLTC is a signal for detectingthat the signal bCIN is at the “H” level, that is, NOP (No Operation) atthe timing of rise of the clock signal, and as shown in the timing chartof FIG. 12, when the command LAL is input at the time of input of thesecond command, the signal bCOLACTW is set to the “L” level based onthree conditions that the signal NOPLTC is set at the “H” level, thesignal bACTUDSB is set at the “L” level and the signal FCWRITE is set atthe “H” level (=RCREAD is set at the “L” level), and if the signalFCREAD is at the “H” level, the signal bCOLACTR is set to the “L” level,and thus, it is possible to detect that the command LAL is input foreach case of the read/write operation. If the command REF or MRS (thedifference therebetween depends on whether the first command is thecommand WRA or the command RDA) is input at the time of input of thesecond command, the signal bCSLTC is set to the “L” level and the signalbACTUDSB is set to the “L” level, and the signals bREFR and bMSET areset to the “L” level according to the state of FCREAD/FCWRITE. Further,at the same time, since the potential of the chip selection pin{overscore (CS)} is set at the “L” level, the signal bACTUDSB is inputto interrupt the operation so as to prevent the command decoder for thefirst command from being operated.

[0071] With the above construction, the following effects (A), (B) canbe attained.

[0072] (A) Since the read/write mode is determined by the first command,not only the operation of the peripheral circuit but also the operationof the memory core can be started at the same time as the row address isfetched, and the random access can be started at earlier time than in acase wherein the start timing of the operation of the memory core isdetermined based on the second command as in the conventional case andthe random access time tRAC is automatically made shorter by one cycle.

[0073] (B) Since the read/write mode is determined by the first command,it is only required to fetch the lower address LA at the time of inputof the second command. Therefore, the process for selecting the columnselection line CSL and outputting data is effected at earlier time thanin the conventional case and the random access time tRAC can beshortened. Further, the word line WL can be early reset and the bit linecan be precharged at earlier time, that is, the random access time tRCcan be shortened by terminating the transfer of data to the peripheralcircuit at earlier time. Thus, both of the random access time tRAC andthe random cycle time tRC can be shortened.

[0074] In FIG. 6, at the time of input of the second command, the chipselection pin {overscore (CS)} is set at the “H” level to latch thelower address LA, and additionally, if the chip selection pin {overscore(CS)} is set at the “L” level, the auto-refresh cycle command REF andmode register set command MRS used in the conventional SDR/DDR-SDRAM aredefined. The above commands are not directly related to this inventionand the detail explanation therefor is omitted.

[0075] A series of above described operations is roughly divided intotwo cases depending on the cycle time tCK. The first one is a casewherein the cycle time tCK is relatively long. If the first command is aread command and the cycle time tCK is sufficiently longer than presettime Tsense (Tsense<tCK) required for selecting a word line WL accordingto the upper address UA, reading out data from the memory cell MC to thebit line pair BL, {overscore (BL)} and amplifying the data by use of thebit line sense amplifier S/A, then the rise of the potential of thecolumn selection line CSL occurs later than the preset time Tsense asshown in FIG. 13A, and therefore, an amount of data on the bit line pairBL, {overscore (BL)} is large enough to transfer the data to the MDQline pair and there occurs no problem.

[0076] On the other hand, if the cycle time tCK becomes shorter, a casewherein the cycle time tCK becomes shorter than Tsense (Tsense>tCK) asshown in FIG. 13B may occur in some cases. In this case, data of thememory cell is not sufficiently amplified by the bit line senseamplifier S/A and if the column selection line CSL is selectedimmediately after the second command is input, division of thecapacitance is rapidly made between the bit line pair and the MDQ linepair and cell data will be destroyed in the worst case. Therefore, ifthe cycle time tCK is short, a so-called gating signal which permits thepotential of the column selection line CSL to be raised after the elapseof the preset time Tsense is used in the internal portion and the risetiming of the potential of the column selection line CSL is shifted tosubstantially the later timing to attain sufficient amplification timefor cell data by the bit line sense amplifier.

[0077]FIG. 14 shows an example of the definition of the random accesstime. tRAC in the first command (read) according to the cycle time tCK.In this example, the random access time tRAC is so set as to becomeshortest (three clocks=22.5 ns) when the cycle time tCK=7.5 ns (133 MHz)and the gating signal CENB is so set as to be enabled approx. 10 nsafter the first command or approx. 2.5 ns after the second command.Approx. 12.5 ns is required for the time Tsense, the potential of thecolumn selection line CSL rises in response to the rise of the gatingsignal CENB and the clock edge of the second command, and after this,data is output based on the above operation.

[0078]FIGS. 15A and 15B show examples of the concrete construction of acircuit for generating the gating signal CENB and FIG. 15C shows anexample of the concrete construction of the column decoder. FIG. 15Ashows a gating signal generating circuit using an RC delay circuit andincluding a P-channel MOS transistor 71, resistor 72, N-channel MOStransistor 73, capacitor 74 and inverters 75, 76, 77. The current pathof the MOS transistor 71, the resistor 72 and the current path of theMOS transistor 73 are serially connected between the power supply andthe ground node. A signal (sense amplifier enable signal) SAE forenabling the operation of the bit line sense amplifier is supplied tothe gates of the MOS transistors 71, 73. One-side electrode of thecapacitor is connected to a connection node of the MOS transistor 71 andthe resistor 72 and the other electrode thereof is connected to theground node. The input terminal of the inverter 75 is connected to theconnection node of the MOS transistor 71 and the resistor 72 and theoutput terminal thereof is connected to the input terminal of theinverter 76. The output terminal of the inverter 76 is connected to theinput terminal of the inverter 77 and the gating signal CENB is outputfrom the output terminal of the inverter 77.

[0079] The gating signal generating circuit shown in FIG. 15B includest-stage (even number of stages) cascade-connected inverters 81, 82, . .. , 8t and the gating signal CENB is output from the final-stageinverter 8t.

[0080] As shown in FIG. 15C, the column decoder includes a NAND gate 91and inverter 92. The input terminals of the NAND gate 91 arerespectively supplied with column address signals CAi(LAi), CAj(LAj), .. . , CAz(LAz) and the gating signal CENB output from the gating signalgenerating circuit shown in FIG. 15A or 15B. An output signal of theNAND gate 91 is supplied to the inverter 92 and a column selectionsignal CSLn is output from the output terminal of the inverter 92.

[0081] With the above construction, the memory core access operation iseffected after input of the first command, the word line is selected andthen a signal (sense amplifier enable signal) SAE for enabling theoperation of the bit line sense amplifier rises. The gating signal CENBis set to the “H” level with delay time corresponding to a period oftime from the rise of the sense amplifier enable signal SAE to the bitline sense operation. The gating signal CENB is supplied to a middleportion of the critical path of the column selection line CSL which isstarted from input of the second command, for example, the columndecoder in an example shown in FIGS. 15A to 15C to control the operationthereof. Thus, by raising the potential of the column selection line CSLaccording to the logical product (AND) of the gating signal CENB and aclock edge after input of the second command, it is possible to read outcell data to the output pin after the stable sense operation is attainedif the cycle time tCK is short and simply raise the potential of thecolumn selection line CSL in response to the clock edge of the secondcommand and output data if the cycle time tCK is long.

[0082] Unlike the case described in the above International Application,data access time from the row access command ACT, that is, random accesstime tRAC does not always take an extra one clock cycle. In addition, anincrease in the logic construction of the internal circuit by making thecommand decoding operation extremely complicated when the row accesscommand ACT and column access command RD are simultaneously input doesnot occur and an increase in the number of input pins of the device doesnot occur. Further, there is no extra delay time which may be consideredto occur in the front half portion of the random access time tRAC. Inaddition, since the command is not complicated, an increase in thepackage size and an increase in the cost will not occur.

[0083]FIGS. 16A, 16B and 17 are timing charts for generally comparingthe conventional system with the system of this invention. FIGS. 16A and16B show the conventional system in which the row access command ACT andupper address UA are input in synchronism with a rise of the clocksignal to operate the row-series peripheral circuit, the column accesscommand RD and lower address LA are input in synchronism with a nextrise of the clock signal to select the word line WL and drive the senseamplifier, and then effect the reset operation and data transferoperation.

[0084] On the other hand, in the system of this invention shown in FIG.17, the read command RDA (or write command WRA) and upper address UA areinput in synchronism with a rise of the clock signal to operate therow-series peripheral circuit, select the word line WL and drive thesense amplifier, and then the lower address LA is input in synchronismwith a next rise of the clock signal to effect the reset operation anddata transfer operation.

[0085] As is clearly understood by comparing the timing charts of FIGS.16 and 17, according to this invention, the speed of the random datareadout operation from the memory cell array can be enhanced withoutdegrading the random access time tRAC.

[0086] As described above, according to this invention, a semiconductormemory device and a data readout method therefor can be attained inwhich the speed of the random data readout operation from the memorycell array can be enhanced without degrading the random access time.

[0087] Further, a semiconductor memory device can be attained in whichthe speed of the random data readout operation from the memory cellarray can be enhanced while the command decoding process is preventedfrom becoming complicated and an increase in the logic construction ofthe internal circuit is suppressed.

[0088] In addition, a semiconductor memory device can be attained inwhich the speed of the random data readout operation from the memorycell array can be enhanced while an increase in the cost due to anincrease in the number of pins and an increase in the package size canbe suppressed.

[0089] Additional advantages and modifications will readily occur tothose skilled in the art. Therefore, the invention in its broaderaspects is not limited to the specific details and representativeembodiments shown and described herein. Accordingly, variousmodifications may be made without departing from the spirit or scope ofthe general inventive concept as defined by the appended claims andtheir equivalents.

What is claimed is:
 1. A semiconductor memory device in which first andsecond commands are input to effect a read/write operation of randomdata with respect to a memory cell array in synchronism with a clocksignal and a row access command and a column access command for datareadout are supplied as one packet in two successive clock cycles,comprising: a first pin supplied with a signal for distinguishing a readcommand and a write command; second pins supplied with upper-side andlower-side decode addresses; a controller to which a signal indicatingthat the read command is input and a signal indicating that the writecommand is input based on the signal input to said first pin aresupplied; a first command decoder controlled by an output signal of saidcontroller, for defining the readout/ write operation by use of thefirst command, fetching an upper-side decode address of a memory cellarray via said second pin and decoding the first command; and alower-side command decoder controlled by an output signal of saidcontroller, for fetching a lower-side decode address of the memory cellarray via the control pin in response to the second command and decodingthe lower-side command.
 2. The semiconductor memory device according toclaim 1, wherein existing pins are also used as said second pins.
 3. Thesemiconductor memory device according to claim 2, wherein said existingpins are a write enable pin and column address strobe pin in anSDR-SDRAM or DDR-SDRAM.
 4. The semiconductor memory device according toclaim 1, further comprising a gating signal generating circuit forcontrolling activation of a column selection line to permit the shortesttime required for amplifying random readout data from the memory cellarray to occur later than a period of time from when the second commandis supplied until the column selection line is selected.
 5. Thesemiconductor memory device according to claim 4, which furthercomprises a column decoder supplied with a column address signal and agating signal output from said gating signal generating circuit, foroutputting a column selection signal to the column selection line and inwhich activation of the column selection line is controlled by thegating signal.
 6. A data readout method for a semiconductor memorydevice in which a row access command and a column access command fordata readout are supplied as one packet in two successive clock cycles,comprising: a first step of inputting a first command in response to achange of a clock signal to define one of readout and write operationsand fetching an upper-side decode address of a memory cell array tooperate a row-series peripheral circuit, select a word line and drive asense amplifier; and a second step of inputting a second command inresponse to a change of the clock signal one clock cycle after thepresent cycle to fetch a lower-side decode address of the memory cellarray, release selection of the word line and transfer data.
 7. The datareadout method for the semiconductor memory device according to claim 6,wherein said first step includes a step of selecting a word lineaccording to the upper-side decode address when a readout operation isinstructed by the first command, a step of reading out data read outfrom the memory cell array to a bit line pair and a step of amplifyingdata read out to the bit line pair by use of a bit line sense amplifier.8. The data readout method for the semiconductor memory device accordingto claim 7, wherein said second step includes a step of releasingselection of the word line, a step of transferring data amplified by thebit line sense amplifier to an MDQ line pair, a step of amplifying dataon the MDQ line pair by use of a DQ read buffer and a step of outputtingdata amplified by the DQ read buffer from an output pin.
 9. A datareadout method for a semiconductor memory device in which first andsecond commands are input to effect a random data readout/writeoperation with respect to a memory cell array in synchronism with aclock signal and a row access command and a column access command fordata readout are supplied as one packet in two successive clock cycles,comprising the steps of: defining one of readout and write operationsand fetching an upper-side decode address of the memory cell array inresponse to the first command; and fetching a lower-side decode addressof the memory cell array in response to the second command.
 10. The datareadout method for the semiconductor memory device according to claim 9,wherein the upper-side and lower-side decode addresses are input toexisting control pins which are used as address pins.
 11. The datareadout method for the semiconductor memory device according to claim10, wherein the existing control pins are a write enable pin and columnaddress strobe pin in an SDR-SDRAM or DDR-SDRAM.
 12. The data readoutmethod for the semiconductor memory device according to claim 10,further comprising the steps of comparing the shortest time required foramplifying random readout data from the memory cell array with a periodof time from when the second command is supplied until the columnselection line is selected; and delaying activation of the columnselection line, when the time taken until the column selection line isselected is earlier than the shortest time required for amplification ofdata.
 13. A data readout method for a semiconductor memory device inwhich first and second commands are input to effect a random datareadout/write operation with respect to a memory cell array insynchronism with a clock signal, comprising the steps of: fetching a rowaddress in response to input of the first command next to a standbystate; and directly supplying a read command (Read with Auto-close)instead of a row access command for starting the operation of aperipheral row-series circuit.
 14. A data readout method for asemiconductor memory device in which first and second commands are inputto effect a random data readout/write operation with respect to a memorycell array in synchronism with a clock signal, comprising the steps of:fetching a row address in response to input of the first command next toa standby state; and directly supplying a write command (Write withAuto-close) instead of a row access command for starting the operationof a peripheral row-series circuit.